The present invention relates generally to digital communications systems, and more specifically to an architecture of a high bandwidth single-stage digital cross-connect switching system.
Digital communications systems are known that employ digital cross-connect switching systems for cross-connection of high speed optical or electrical signals in broadband communications networks. Conventional digital cross-connect switching systems typically have either a single-stage or multi-stage switching architecture. For example, a conventional single-stage cross-connect switching architecture may comprise at least one multi-port Random Access Memory (RAM) such as a Single Write Many Read (SWMR) multi-port RAM or a Many Write Single Read (MWSR) multi-port RAM. The SWMR or MWSR multi-port RAM typically includes a first plurality of Flip-Flops (FFs) for storing input data, a plurality of selectors for sorting the data according to a predetermined switching configuration, and a second plurality of FFs for storing output data. Further, whereas the SWMR multi-port RAM is typically configured to write the input data into storage as it arrives, and read the sorted output data according to the predetermined switching configuration, the MWSR multi-port RAM typically sorts the input data as it arrives, writes the sorted data into storage, and then sequentially reads the sorted output data.
One drawback of the conventional single-stage cross-connect switching architecture including the SWMR or MWSR multi-port RAM is that as the number of ports increases, the number of combinatorial logic gates required for sorting the data also increases. Further, as the number of combinatorial logic gates increases the number and lengths of lines required to interconnect the logic gates typically increase, thereby expanding the area required to layout the selectors. This can be problematic when implementing the SWMR or MWSR multi-port RAM on an Application Specific Integrated Circuit (ASIC) because the expanded layout area can increase the die size requirements, which in turn can lead to higher manufacturing costs.
The conventional multi-stage cross-connect switching architecture may comprise a three-stage Clos architecture, in which the cross-connect switching system includes a first group of switches in an input stage, a second group of switches in a center stage, and a third group of switches in an output stage. For example, a three-stage Clos architecture configured to interconnect N input ports and N output ports may include N/n n-by-k switches in the input stage, k N/n-by-N/n switches in the center stage, and N/n k-by-n switches in the output stage. Further, for most cross-connection requirements, the three-stage Clos architecture is non-blocking, i.e., any input port can connect to any output port without preventing any other input port from connecting to any other output port.
However, the conventional three-stage Clos architecture also has drawbacks in that the architecture can block when required to make some advanced multicast connections. For example, overlapping multicast connections in the three-stage Clos cross-connect system can sometimes leave stranded bandwidth in different parts of the network, which may prevent a desired cross-connection between selected input and output ports. It can also be difficult to assure that the three-stage Clos cross-connect system remains non-blocking when implementing certain protection switching schemes.
It would therefore be desirable to have an architecture of a high bandwidth digital cross-connect switching system that has a simpler and more compact layout. Such a cross-connect architecture would employ a switch fabric that is internally non-blocking. It would also be desirable to have a cross-connect architecture that can be implemented on one or more ASICs with a reduced number of logic gates.